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d a t a sh eet product speci?cation file under integrated circuits, ic01 september 1989 integrated circuits SAA7500 digital satellite radio broadcasting tuner decoder (sat-2)
september 1989 2 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 general description the SAA7500 performs a decoder function for digital satellite sound broadcasting tuners. it is designed to decode one of 16 stereo channels broadcasting audio signals in accordance with the german standard - technische richtlinie ard/zdf nr. 3r1 . features clock recovery differential decoding main frame synchronization swapping half-frames in case of inversion unscrambling demultiplexing subframe synchronization error correction and concealment scale factor decoding with error correction shift into the original values using the scale factors mute in case of synchronization loss quick reference data package outline 68-lead plastic leaded chip carrier (plcc); pocket version (sot188aa); sot188-2; 1996 september 05. parameter symbol min. max. unit supply voltage v dd 4.5 5.5 v power dissipation p tot 500 mw clock frequency t 20n 20.48 mhz
september 1989 3 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 fig.1 block diagram.
september 1989 4 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 pinning fig.2 pinning diagram; for pin functions see next page.
september 1989 5 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 pin functions (1) = cmos level input. (2) = ttl level input. (3) = cmos level input with pull down resistor. pin no. mnemonic description 1 lza i(3) phase adjustment for the internal clock. 2 lzb i(3) phase adjustment for the internal clock. 3 lzc i(3) phase adjustment for the internal clock. 4 sto i(3) control input for testing. 5 t20n i(1) 20.48 mhz clock input from voltage controlled oscillator (vcx). 6 lzd i(3) control input for testing. 7 lze i(3) control input for testing. 8 phd o phase control signal for vcx. 9 lzf i(3) control input for testing. 10 kus o test output (ab swap). 11 syln o synchronization indication ?ag. 12 pd i(2) programme number input selector (msb). 13 pc i(2) programme number input selector. 14 pb i(2) programme number input selector. 15 pa i(2) programme number input selector (lsb). 16 upmu i(2) mute input (controlled by microcomputer). 17 intr o interrupt ?ag for microcomputer. 18 tup o programme type interface (clock). 19 paup o programme type interface (data). 20 r32 o multiplex control signal for right channel. 21 l32 o multiplex control signal for left channel. 22 dwca i(3) da-converter mode select input. 23 dwcb i(3) da-converter mode select input. 24-33 b16-7 o audio data for parallel interface, bits 16 (lsb) to 7. 34 v ss1 i ground (supply). 35-40 b6-1 o audio data for parallel interface, bits 6 to 1 (msb). 41 oosc o 4.096 mhz clock output. 42 acm o concealment ?ag (for saa7220p/c). 43 awd o audio data (for saa7220p/c). 44 awt o bit clock (for saa7220p/c). 45 awr o word select signal (for saa7220p/c). 46 amun o mute signal (for saa7220p/c). 47 dic o data output for testing. 48 die o data output for testing.
september 1989 6 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 49 tfkn o burst clock for test data. 50 m2n i(2) channel mode select input. 51 m1n i(2) channel mode select input. 52 pid o programme information (pi) interface output (data). 53 pif o programme information (pi) interface output (window signal). 54 pitn o programme information (pi) interface output (clock). 55 n.c. not connected. 56 asc o data output for 10.24 mbit/s interface. 57 bsc o data output for 10.24 mbit/s interface. 58 fsy o window signal for 10.24 mbit/s interface. 59 t10n o 10.24 mhz clock output. 60 n.c. not connected. 61 swa i(2) 10.24 mbit/s data input. 62 v ss2 i ground (screen). 63 swb i(2) 10.24 mbit/s data input. 64 mcr i(1) master reset. 65 st1 i(3) control input for testing. 66 st2 i(3) control input for testing. 67 st3 i(3) control input for testing and mode select for 10.24 mbit/s interface. 68 v dd i power supply. pin no. mnemonic description
september 1989 7 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 functional description general the SAA7500 has been designed to decode 16 stereo channel sound broadcasting signals in accordance with the german standard - technische richtlinie ard/zdf nr. 3r1 . the channel carrying the sound broadcast programme is selected and converted into an intermediate frequency by a frontend. the signal is then amplified and demodulated (4 psk (phase shift keying) with carrier recovery). the outputs from the demodulator are two differential coded signals that are input into the SAA7500. the SAA7500 decoder outputs the audio data, of the selected stereo or mono channel, as linear quantized 16-bit audio samples. selection of the desired audio channel, as well as stereo or mono mode, is controlled by inputs pa, pb, pc and pd. these inputs may be driven directly by switches or controlled by a microcomputer. when under the control of a microcomputer, the SAA7500 transmits serial data to the microcomputer on the type of programme (16 stereo or 32 mono). the corresponding synchronization of the subframe is partly performed by the SAA7500 (every 2 ms) and at a higher level by the microcomputer (every 16 ms). the SAA7500 also sends to the microcomputer, programme information code data together with its clock and window signal. the circuit automatically performs the system error correction and concealment. in the transmit error rate range of 0 to 3 10 -3 a theoretical c/n (carrier-to-noise ratio) gain of about 6 db is obtained. the residual error rate is nearly zero for transmit error rates 3 10 -4 . the remaining functions, such as clock recovery, main and subframe synchronization and scale factor decoding, are protected in a similar manner so that they will not influence the residual error rate. clock recovery the baseband signals a and b are connected to the swa and swb inputs of the SAA7500. for clock recovery, the phase of the incoming data streams is compared with t10n (half the oscillator frequency). the output of the phase comparator (phd) controls, by means of the loop filter, the voltage controlled oscillator (both are external to the ic) and thus its output signal t20n. for energy dispersal, for example, in modulation pauses or with constant signals, the data streams are scrambled during generation. the exceptions are the synchronization words and the special service bits. in order that the phase correspondence between the recovered system clock (t10n) and the input signals a and b can be adjusted to a minimum bit error rate (ber), a programmable phase shifter is provided (inputs lza, lzb, lzc and st3). the differential decoder logic delivers the original data streams which may be exchanged depending on the number of mixer stages on the transmission channel. the polarity of the two synchronization words will indicate if this is necessary, if so the two data streams will be automatically switched over. synchronization using the synchronization circuit, the incoming data streams are first searched for 11-bit barker codewords. the synchronization circuit permits two errors for both synchronization words, which guards against failure of the synchronization word. if the synchronization word has been detected, the following data is examined at frame length intervals to see if the synchronization word is repeated. if it is repeated, it is acknowledged as a synchronization word (window check) and an internal frame pulse generator takes over further control. there is also synchronization word failure control which initiates a renewed synchronization word search and mutes the af output if four successive synchronization word failures occur. to enhance the performance the result from the error correction circuit is used as an additional input to the synchronization circuit. this is to avoid extra errors through synchronization loss in the case of relative high, but for reception acceptable, bit error rates. this will not affect the rapid detection of a very high bit error rate or the non-synchronization of the data stream. the decoder will function correctly with a bit error rate up to 3 10 -3 .
september 1989 8 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 demultiplexer after synchronization, the beginning of a frame is marked and the digital signals are defined as to their assignment. first the non-scrambled special service bit from the half frame a is taken out. the rest of both half frames are unscrambled and demultiplexed so that each half frame is split into two substreams with a rate of 5.12 mbit/s (see technische richtlinie ard/zdf nr. 3r1, main frame specification). using the inputs from the synchronization circuit and the programme selector (inputs pa, pb, pc and pd) the demultiplexer locks on to the selected programme block and generates all the control signals required for further signal processing. error correction the error correction circuit provides for exact identification of two errors in a 63/44 bch block and correction of the incorrect bits. in the event of more than two errors the identification circuit can identify incorrect bch blocks with up to five errors. the bch block is operated on by a syndrome calculator, the results controls the lines of an error correction matrix. the output of this matrix corrects (inverts) the incorrect bits when data is shifted out from its buffer. the bch block is then fed through a second syndrome calculator. in the event of more than two errors the result of the whole calculation will be other than zero. this information provides the concealment in the next stages. the two adjacent samples related to the detected incorrect sample are added and divided by two, the result replaces the incorrect sample (interpolation). in the event of successive bad samples the last corrected sample is held until a good sample is detected (hold function). a high error frequency in the event of synchronization loss will activate the muting function and set the output data to zero. this information, if concealment is not active, is used in the synchronization circuit as described in that section. when the samples are correct it can be assumed that the synchronization is also correct. scale factor, programme type evaluation and shift sunction the transmitted samples are returned to their original range of values by the scale factor, which is obtained by decoding the zi-subframe. the start of this frame is coupled to the start of the special services frame, synchronization for this frame uses the same principle as for the main frame. in the scale factor evaluation unit the bch 14/6 code words (three times transmitted) are fed into a majority selection circuit working at bit level. subsequently the error check and the correction of a maximum of two errors is carried out. the SAA7500 contains the synchronization word detection and error check for the subframe synchronization word with its repetition time of 2 ms. the programme type evaluation with its superior synchronization has to be performed external to the chip, for example, by a microcomputer. for this purpose data is available in 8-bit blocks at a serial interface (intr, paup and tup; block rate = 4000/s). the same microcomputer can also perform the programme selection (inputs pa, pb, pc and pd). at the input to the concealment buffer the corrected 11 bits (msb) are combined with the 3 unprotected transmitted bits (lsb). the scale factor determines the required shift-back operations needed to convert the transmitted values back into the original values. voids that occur are filled with noughts or ones corresponding to the sign bit. the shift-back and filling of voids ensures that no incorrect bits occur above the range defined by the scale factor. the upper 16 bits represent the regenerated audio sample.
september 1989 9 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 digital-to-analogue conversion and interfaces the SAA7500 enables different dac systems to be used. for control of the saa7220p/c and tda1541 a 2.5 external divider must be connected to the 20.48 mhz clock signal to produce the required 8.192 mhz clock signal. a serial interface is built in with the following outputs: bit clock (awt), word select (awr) and audio data (awd). in addition the mute signal (amun) and the concealment flag (acm) are also available. the saa7220p/c and tda1541 are equipped with a digital audio interface for domestic use equivalent to iec proposal no. 84 (secretariat 28; from june 1985). for dacs with a parallel interface in a multiplex mode the audio data are available at the b1(msb)-b16 outputs. the multiplexing is controlled by the l32 and r32 outputs. using the mode outputs dwca and dwcb the code (offset binary or twos complement) and polarity can be selected. additional information, including the scale factor is available through the programme information (pi) interface (pid, pitn, and pif). another interface, using the asc, bsc and t10n outputs, makes available signals from the differential decoder. these signals are used for bit error measurement and an optimized phase adjustment of the internal clock (refer to clock recovery section). an optional application of the control signals for mute and concealment operations is possible using the outputs amun and acm. for the mute signal a different time relationship to the unwanted pulse with very low c/n values may be obtained. the external application of the concealment signal is recommended; if an additional interpolation is required between additional samples with different levels in the external circuitry (such as the saa7220p/c). truth tables table 1 delay adjustment pins 1 to 3 t ? 1.5 gate delay time (nand) lzc lzb lza delay 0004 t 0013 t 0102 t 0111 t 1000 t 101 - 1 t 110 - 2 t 111 - 3 t table 2 master reset pin 64 table 3 mute pin 16 mcr function 0 operation 1 master reset upmu function 0no 1 yes
september 1989 10 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 table 4 programme number pins 12 to 15 table 5 phase control signal pin 8 table 6 synchronization indication pin 11 table 7 mode select for data outputs asc and bsc for 10.24 mbit/s interface pin 67 table 8 data converter mode select b1 (msb) to b16 pins 22 and 23 pd pc pb pa programme no. 00001 00012 00103 ..... 110114 111015 111116 phd phase 0 lead phase 1 lag phase syln synchronization 0 yes 1no st3 data asc/bsc 0 after unscrambler 1 before unscrambler dwcb dwca da converter mode 0 0 compl. offset binary 0 1 offset binary 1 0 compl. 2s complement 1 1 2s complement table 9 channel mode select pins 50 and 51 table 10 concealment pin 42 table 11 mute pin 46 table 12 interrupt pin 47 m2n m1n channel mode 0 0 mono (1 + 2) 0 1 mono r(2) 1 0 mono l(1) 1 1 stereo acm function 0no 1 yes amun mute 0 yes 1no intr interrupt 0no 1 yes
september 1989 11 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 ratings limiting values in accordance with the absolute maximum rating system (iec 134) note 1. v dd + 0.5 must not exceed 7.0 v. handling inputs and outputs are protected against electrostatic charge in normal handling, however, to be totally safe it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices). the plcc-68 package can only be guaranteed with soldering temperatures up to a maximum of 235 c. parameter symbol min. max. unit supply voltage range v dd - 0.5 7.0 v input voltage range (1) v i - 0.5 v dd +0.5 v input current i i - 10 ma output current i o - 10 ma supply current in v ss i ss - 28 ma supply current in v dd i dd - 28 ma total power dissipation p tot - 500 mw operating ambient temperature range t amb - 25 +85 c storage temperature range t stg - 55 +150 c
september 1989 12 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 dc characteristics t amb = 0 c to + 70 c; unless otherwise speci?ed notes to dc characteristics 1. t amb = 25 c, all inputs at v ss or v dd , all outputs open. 2. at 25 c max. 1 m a. parameter conditions symbol min. typ. max. unit supply voltage v dd 4.5 - 5.5 v supply current fig.10 i dd - 12.5 - ma quiescent supply current note 1 i ddq -- 50 m a inputs i(1) input voltage low v il -- 0.3 v dd v input voltage high v ih 0.7 v dd -- v input current low note 2 - i il -- 10 m a input current high note 2 i ih -- 10 m a inputs i(2) input voltage low v il -- 0.8 v input voltage high v ih 2.0 -- v input current low note 2 - i il -- 10 m a input current high note 2 i ih - -10 m a inputs i(3) input voltage low v il -- 0.3 v dd v input voltage high v ih 0.7 v dd -- v pull down resistor r i 25 50 100 k w outputs o output voltage low - i ol = 1 ma v ol -- 0.5 v output voltage high i oh = 1 ma v oh 4.0 -- v
september 1989 13 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 ac characteristics t amb = 0 to + 70 c; unless otherwise speci?ed notes to the characteristics 1. due to noise, the period t swl may occasionally vary between 30 and 70 ns. 2. due to noise, the period time t psw may occasionally vary between 77.6 and 117.6 ns. parameter conditions symbol min. typ. max. unit t20n clock pulse fig.3 pulse width high t wh 15 20 - ns pulse width low t wl 15 22 - ns t20n pulse period t p20 48 48.8 - ns data input timing fig.4 set-up time for data swa and swb to t10n note 1 t swl - 50 - ns t10n pulse period t psw note 2 t p10 - 97.6 - ns main frame timing fig.5 main frame sync pulse t sync - 11t p10 - ns audio data timing fig.6 audio sample repetition time t samp - 31.25 - m s load pulse width high t lph - 6.25 - m s audio data hold t adh - 1- m s i 2 s timing fig.7 frequency awt signal f awt - 1.024 - mhz audio sample repetition time t samp - 31.25 -m s pi interface timing fig.8 frequency pitn signal f pitn - 32 - khz pitn pulse period t pitn - 31.25 -m s pif pulse width high t pifh - 22t pitn -m s pif pulse period t zi - 2 - ms output timing programme type interface fig.9 intr pulse period t intr - 250 -m s intr pulse width high t pinh - 31.25 -m s
september 1989 14 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 fig.3 waveform at clock input t20n (pin 5). fig.4 data input timing (pins 59, 61 and 63). fig.5 output timing for 10.24 mbit/s interface (pins 56, 57, 58 and 59).
september 1989 15 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 fig.6 audio data timing parallel out (pins 40 to 35, 33 to 24, 21 and 20). fig.7 inter-ic sound (i 2 s) timing and mute and interpolation flags (pins 42 to 46).
september 1989 16 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 fig.8 pi interface timing (pins 52 to 54). fig.9 output timing programme type interface (pins 17 to 19). (1) programme type - left (2) programme type - right (3) this time is approximately 10 m s
september 1989 17 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 fig.10 application proposal.
september 1989 18 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 package outline references outline version european projection issue date iec jedec eiaj note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. sot188-2 44 60 68 1 9 10 26 43 27 61 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k 1 k x y e e b d h e h v m b d z d a z e e v m a pin 1 index 112e10 mo-047ac 0 5 10 mm scale 92-11-17 95-03-11 plcc68: plastic leaded chip carrier; 68 leads sot188-2 unit a a min. max. max. max. max. 1 a 4 b p e (1) (1) (1) eh e z y w v b mm 4.57 4.19 0.51 3.30 0.53 0.33 0.021 0.013 1.27 0.51 2.16 45 o 0.18 0.10 0.18 dimensions (millimetre dimensions are derived from the original inch dimensions) d (1) 24.33 24.13 h d 25.27 25.02 e z 2.16 d b 1 0.81 0.66 k 1.22 1.07 k 1 0.180 0.165 0.020 0.13 a 3 0.25 0.01 0.05 0.020 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.958 0.950 24.33 24.13 0.958 0.950 0.995 0.985 25.27 25.02 0.995 0.985 e e e d 23.62 22.61 0.930 0.890 23.62 22.61 0.930 0.890 0.085 0.032 0.026 0.048 0.042 e e inches d e
september 1989 19 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all plcc packages. the choice of heating method may be influenced by larger plcc packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all plcc packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
september 1989 20 philips semiconductors product speci?cation digital satellite radio broadcasting tuner decoder (sat-2) SAA7500 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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